-- full adder as half adders and or

type Bit = int 1;

box gen
in (t::int 64)
out (t'::int 64,x,y,c::Bit)
match
 0 -> (1,0,0,0) |
 1 -> (2,0,1,0) |
 2 -> (3,1,0,0) |
 3 -> (4,1,1,0) |
 4 -> (5,0,0,1) |
 5 -> (6,0,1,1) |
 6 -> (7,1,0,1) |
 7 -> (0,1,1,1);

template half2
in (x,y::Bit)
out (s,c::Bit)
match
 (0,0) -> (0,0) |
 (0,1) -> (1,0) |
 (1,0) -> (1,0) |
 (1,1) -> (0,1);

instantiate half2 as h * 2;

box or
in (x,y::Bit)
out (z::Bit)
match
 (0,0) -> 0 |
 (0,1) -> 1 |
 (1,0) -> 1 |
 (1,1) -> 1;

box show
in (s,c::Bit)
out (sc::(Bit,Bit,char))
match
 (s,c) -> (s,c,'\n');

stream output to "std_out";

wire gen (gen.t' initially 0) (gen.t,h1.x,h1.y,h2.x);
wire h1 (gen.x,gen.y) (h2.y,or.x);
wire h2 (gen.c,h1.s) (show.s,or.y);
wire or (h1.c,h2.c) (show.c);
wire show (h2.s,or.z) (output);