-- half adder as xor and and

type Bit = int 1;

box gen
in (t::int 64)
out (t'::int 64,x,y::Bit)
match 
 0 -> (1,0,0) |
 1 -> (2,0,1) |
 2 -> (3,1,0) |
 3 -> (0,1,1);

box fanout
in (x,y::Bit)
out (x1,y1,x2,y2::Bit)
match
 (x,y) -> (x,y,x,y);

box xor
in (x,y::Bit)
out (z::Bit)
match
 (0,0) -> 0 |
 (0,1) -> 1 |
 (1,0) -> 1 |
 (1,1) -> 0;

box and
in (x,y::Bit)
out (z::Bit)
match
 (0,0) -> 0 |
 (0,1) -> 0 |
 (1,0) -> 0 |
 (1,1) -> 1;

box show
in (z,c::Bit)
out (zc::(Bit,Bit,char))
match 
 (z,c) -> (z,c,'\n');

stream output to "std_out";

wire gen (gen.t' initially 0) (gen.t,fanout.x,fanout.y);
wire fanout (gen.x,gen.y) (xor.x,xor.y,and.x,and.y);
wire xor (fanout.x1,fanout.y1) (show.z);
wire and (fanout.x2,fanout.y2) (show.c);
wire show (xor.z,and.z) (output);