The interaction between memory management and concurrency poses a particular challenge in exploiting modern, increasingly parallel hardware. Both language support and runtime-system support for concurrency needs to be integrated with highly optimised memory management policies in order to provide a high level programming model to the programmer. This one-day workshop aims to bring together UK academia and industry with the aim of establishing new links and enhancing existing collaboration within the framework of the UK Memory Management Network.

The UK Memory Management Network provides researchers from academia and industry with a unique opportunity to meet, to discuss challenges, state-of-the-art techniques and solutions, and to exchange ideas and experiences. MMNet'13 will take place at Heriot-Watt University, Edinburgh, on Wednesday 8th May 2013. We call for contributions in any aspect of memory management including

• virtual machine implementation
• garbage collection algorithms
• performance tuning techniques
• empirical studies of dynamic behaviour
• abstractions and models for memory management
• runtime support for concurrency
• language support for concurrency
• transactional memory

Note that since this is an informal workshop, an MMNet presentation will not prevent publication elsewhere. Event registration is free, thanks to generous sponsorship from EPSRC and SICSA.

A list of previous workshops gives an indication of topics covered in this series.

Important Dates

• 29th April: Registration deadline
• last-minute registration by email to Hans-Wolfgang Loidl
• 8th May: MMnet'13 Workshop

When:

Where:

Follow these travel instructions and find us on this on-line campus map (Earl Mountbatten Buildings) or this pdf campus map (Earl Mountbatten Buildings are (21) on this map).

The venue is Heriot-Watt University, Riccarton Campus, Earl Mountbatten Building, Room EM 1.82, which is building 2 on this map, with entrance from Boundary Road North.

The best connection from the city centre is Bus 25 (passing Waverly as well as Haymarket train stations) to Riccarton, which stops just in front of the receiption at the university, or Bus 34 (passing Waverly train station), which stops directy in front of the department (north entrance).

Schedule

We plan for MMNet'13 to start around 11:00 on Wed 8 May, and finish by 17:30. We will post the official meeting schedule up here once it is finalised. Talks will be either 15 minutes or 30 minutes, including time for questions. Lunch and refreshments will be provided throughout the day.

Schedule with abstracts.

Schedule for the day (all in EM 1.82):

10:30-11:00		Arrival and Coffee
11:00-11:30	Tim Harris	Rethinking the stack for distributed runtime systems (abstract, slides)
11:30-12:00	Lokesh Gidra	A study of the Scalability of Stop-the-World Garbage Collectors on Multicore (abstract, slides)
12:00-12:30	Susmit Sarkar	From C/C++11 to Power and ARM: What is Shared-Memory Concurrency Anyway? (abstract, slides)
12:30-13:30		Lunch
13:30-14:00	Jeremy Singer	Control Theory for Adaptive Heap Resizing (abstract, slides)
14:00-14:30	David Matthews	Parallel GC and Heap Management in Poly/ML and Isabelle (abstract, slides)
14:30-15:00	Sven-Bodo Scholz	Efficient Reference Counting for Nested Task- and Data-Parallelism (abstract, slides)
15:00-15:30		Coffee
15:30-16:00	Richard Jones	Rigorous Benchmarking in Reasonable Time (abstract, slides)
16:00-16:30	Kevin Hammond	Automatic amortised analysis of dynamic memory allocation for lazy functional programs (abstract, slides)
16:30-17:00	Paul Keir	Visualising DMA Operations for Improved Parallel Performance (abstract, slides)
17:00-17:15	Malak Aljabri	The Design and Implementation of Scalable Parallel Haskell (abstract, slides)
17:15		Closing

Contact

If you have any questions about the workshop or the MMnet network please contact:

• Hans-Wolfgang Loidl (MMnet'13 organiser)
• Richard Jones (MMnet chair)

Sponsors

Attendance of MMnet'13 is free thanks to sponsorship of the MMnet network by EPSRC and by SICSA. MMnet'13 is hosted by the Dependable Systems Group at Heriot-Watt University.